M5M5165P-10L

M5M5165P-10L

-package: DIP-28

-Brand : MITSUBISHI

The operation mode of the M5M5165P, FP is determined by a combination of the device control inputs Si, S2, Wand OE. Each mode is summarized in the function table. (see next page) A write cycle is executed whenever the low level W overlaps with the low level Si and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W, Si or S2, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The Output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while S1 and S2 are in an active state (SI=L,