EP1810J-145

The Altera Classic’ devtcc family offers a solution to high-speed, low-power logic integration. Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version, which is described in this data sheet.
Classic devices support 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates. The Classic family provides pin-to-pin logic delays as tow as 10 ns and counter frequencies as high as 10(1 MI lz. Classic devices are available in a wide range of packages, including CerDIP, PDIP, PLCC, PGA, and SOIC packages.
EPROM-based Classic devices can reduce active power consumption without sacrificing performance_ This reduced power consumption makes the Classic family well suited for a wide range of low-power applications. Classic devices are 100% genencally tested and can he erased with ultra-violet (UV) light, allowing design changes to be implemented quickly.
Classic devices use sum-of-products logic and a programmable register. The sum-of-products logic provides a programmable-AD/fixed-OR structure that can implement logic with up to eight product terms. Thu programmable register can be individually programmed for 13, T, SR, or JK flipflop operation or can be bypassed for combinatorial operation. In addition, macrocell registers can be individually clocked either by a global clock or by any input or feedback path to the AND array. Altera’s proprietary programmable I/O arthitecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to implement a variety of logic functions simultaneously.

Classic devices are supported by Altera’s MAX+PLUS II development system, a single, integrated package that offers schematic, text—including VHDL, Vertlog HDL, and the Altera Hardware Description Language (Al IDL)—and waveform design entry; compilation and logic synthesis; simulation and timing analysis; and device programming. The MAXI-PLUS lI software provides EDIF 20 0 and 30 0, LIN, VHDL„ Verilog I ILL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and workstation-based FDA tools. The MAX+PLUS 11 software runs on 486- and Pentium-based PCs, and Sun SPARC.station, HP 90t1) Series 700/80U, and IBM RISC System/6000 workstations. These devices also contain on-board logic test circuitry to allow verification of function and AC specifications during standard production flow.