SAE81C52P

The SAE 81C52 is a CMOS-silicon gate, static random access memory (RAM), organized as 256 words by 8 bits. The multiplexed address and data bus interfaces directly to 8-bit microprocessors/microcontrollers without any timing or level problems, e.g. the families SAB 8086, SAB 8051.

All inputs and outputs are fully compatible with NMOS circuits, except CS1. Data retention is ensured up to VDD ≥ 1.0 V. The SAE 81C52 has three different inputs for two chip select modes which allow to inhibit either the address/data lines (AD 0 … AD 7) and the control lines (WR, RD, ALE, CS2, CS3), or only the control lines RD, WR.

The power consumption is max. 5.5 μW in standby mode and max. 16.5 mW in operation. In standby mode, the power consumption will not increase if the control inputs are on undefined potential.