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— 10 ns military and industrial versions 7 ns tCO
6 ns tS
10 ns tPD
110-MHz state machine
— 15-ns commercial, industrial, and military versions— 25-ns commercial, industrial, and military versions
The Cypress PALCE22V10 is a CMOS Flash-erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-products (AND-OR) logic structure and the programmable macrocell.
The PALCE22V10 is executed in a 24-pin 300-mil molded DIP, a 300-mil cerDIP, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 10 outputs. The PALCE22V10 can be electrically erased and reprogrammed. The program- mable macrocell provides the capability of defining the archi- tecture of each output individually. Each of the ten potential outputs may be specified as “registered” or “combinatorial.” Polarity of each output may also be individually selected, allowing complete flexibility of output configuration. Further configurability is provided through “array” configurable “output enable” for each potential output. This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled by the programmable array.PALCE22V10 features a variable product term architecture. There are 5 pairs of product term sums beginning at 8 product terms per output and incrementing by 2 to 16 product terms per output. By providing this variable structure, the PALCE22V10 is optimized to the configurations found in a majority of applications without creating devices that burden the product term structures with unusable product terms and lower performance.Additional features of the Cypress PALCE22V10 include a synchronous preset and an asynchronous reset product term. These product terms are common to all macrocells, elimi- nating the need to dedicate standard product terms for initial- ization functions. The device automatically resets upon power-up.
The PALCE22V10, featuring programmable macrocells and variable product terms, provides a device with the flexibility to
implement logic functions in the 500- to 800-gate-array complexity. Since each of the ten output pins may be individ- ually configured as inputs on a temporary or permanent basis, functions requiring up to 21 inputs and only a single output and down to twelve inputs and ten outputs are possible. The ten potential outputs are enabled using product terms. Any output pin may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output. Each of these outputs is achieved through an individual program- mable macrocell. These macrocells are programmable to provide a combinatorial or registered inverting or non-inverting output. In a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array. This information is available for estab- lishing the next result in applications such as control state machines. In a combinatorial configuration, the combinatorial output or, if the output is disabled, the signal present on the I/O pin is made available to the array. The flexibility provided by both programmable product term control of the outputs and variable product terms allows a significant gain in functional density through the use of programmable logic.
Along with this increase in functional density, the Cypress PALCE22V10 provides lower-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability.
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تهران -خ جمهوری - پاساژ امجد - طبقه زیر همکف - شماره 25
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