CDP1854ACE

CDP1854ACE

package:DIP-40

INTERSIL

Two Operating Modes – Mode 0 – Functionally Compatible with Industry Types Such as the TR1602A and CDP6402 – Mode 1 – Interfaces Directly with CDP1800-Series Microprocessors without Additional Components Full or Half Duplex Operation Parity, Framing and Overrun Error Detection Baud Rate to 200K Bits/s at VDD. to 400K Bits/s at VDD. 10V Fully Programmable with Externally Selectable Word Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and or 2 Stop Bits False Start Bit Detection

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

VDD 1 MODE (VSS) 2 VSS 3 RRD 4 R BUS 5 R BUS 6 R BUS 7 R BUS 8 R BUS 9 R BUS 10 R BUS 11 R BUS OE 15 SFD 16 R CLOCK 17 DAR DA 19 SDI 40 T CLOCK 39 EPE 38 WLS 1 37 WLS 2 36 SBS PI 34 CRL 33 T BUS 32 T BUS 31 T BUS 30 T BUS 29 T BUS 28 T BUS 27 T BUS 26 T BUS SD0 24 TSRE 23 THRL 22 THRE 21 MR

VDD 1 MODE (VDD) 2 VSS 4 R BUS 5 R BUS 6 R BUS 7 R BUS 8 R BUS 9 R BUS 10 R BUS 11 R BUS 0 12 INT FE 14 PE/OE 15 RSEL 16 R CLOCK 17 TPB DA 19 SDI = NO CONNECT 40 T CLOCK 39 CTS CS3 34 RD/WR 33 T BUS 32 T BUS 31 T BUS 30 T BUS 29 T BUS 28 T BUS 27 T BUS 26 T BUS SD0 24 RTS CS1 22 THRE 21 CLEAR

NOTE: MODE 0(MODE 1) SFD (RSEL) R CLOCK MR(CLEAR) THRE(THRE) TSRE(RTS) DA(DA) SDI NC THRL(CS1) (TPB)DAR SD0

TRANSMITTER SECTION T CLOCK CDP1802 INTERFACE RD/WR RSEL RECEIVER SECTION R CLOCK 2 = VDD 3 = VSS 21 = CLEAR = NC

NOTE: 1. User Interconnect FIGURE 1. MODE 1 BLOCK DIAGRAM (CDP1800-SERIES MICROPROCESSOR COMPATIBLE)