PAL20L10ACNS

The PAL20X10A Series offers Exclusive-OR gates pre-ceding each flip-flop. The XOR gate combines two sum terms, each composed of two product terms. This extra level of logic is very efficient for counter applications. The combinatorial member of the family, the PAL20L1 0, offers three product terms per output with no XOR gate. A fourth product term provides the enable term. While the registered devices are offered in only one perform-ance option, the 20L10 is offered in four performance grades. Note that three of these options follow the “old” AMD part numbering system while the fourth follows the “old” MMI part numbering system, as do the registered devices.
The family utilizes Advanced Micro Devices’ advanced bipolar process and fuse-link technology. The devices provide user-programmable logic for replacing conven-tional SSI/MSI gates and flip-flops at a reduced chip count.
The family allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function. Complex interconnections be-tween gates, which previously required time-consuming layout, are lifted from the PC board and placed on sili-con, where they can be easily modified during prototyp-ing or production. The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. In addition, the PAL device provides the follow-ing options: — Variable input/output pin ratio — Programmable three-state outputs — Registers with feedback Product terms with all fuses opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. Registers consist of D-type flip-flops that are loaded on the LOW-to-HIGH transition of the clock. Un-used input pins should be tied to Vcc or GND. The entire PAL device family is supported by the PALASM software package. The PAL family is pro-grammed on conventional PAL device programmers with appropriate personality and socket adapter mod-ules. See the Programmer Reference Guide for ap-proved programmers. Once the PAL device is pro-grammed and verified an additional fuse maybe opened to prevent pattern readout. This feature secures proprie-tary circuits.