AM7971A-3JCThe Am797IA Compression Expansion Processor (CEP) with Image Bit-Boundary Processing capacity is a high performance peripheral which compresses and expands two-tone bit mapped images or documents in accordance with internationally accepted CCITT standards. These fully image preserving algorithms reduce storage requirements and data transmission time for systems handling bit-mapped data.
The Am7971A is a functionally enhanced version of the Am7971 offering improved negative compression and error recovery performance. The Am7971A can replace the Am7971 in existing systems without board/system/timing alterations.
The Am7971A performs onedirnonsional Modified Hoff-man (MR) run-length coding as well as two-dimensional Modified READ (MR/MMR) relative coding as specified in CCITT Recommendations T.4 and T.6 for Group III and Group IV compatible equipments. The typical compression ratio for the eight CCITT test documents is 51 to 50:1. The compressor and expander operate not only In full duplex mode but each processor can be indopendenUy programmed for ono-dimensional encoding/decoding, two-dimensional encoding/decoding, or transparent data trans-fer.
Equipped with an On•Cha) error detection mechanism, the Am7971A detects data corruptions by checking for illegal codes, negative run-lengths and incorrect line lengths.
Furthermore. its architecture allows for error recovery with minimal CPU intervention. With 46 user programmable registers, standard Arn8088- like microprocessor bus interface, dual bus architecture and on-chip DMA the Am7971A offers tremendous system flexibility and ease of implementation. After initialization tho Am7971A will operate with minimal CPU overhead. Its status is available through polled registers and exception conditions may be signalled using an external interrupt. Document page width is programmable up to 16K picture elements (pets). Programmable frame width enable win-dowing features and programmable top, left and right margins allow image boundaries to be left blank. Optional express mode allows one line to be skipped after every ‘nth’ line to accelerate compression (n 1 to 255). On the expansion side, the granularity option allows the processor to duplicate every mth line (m 1 to 7). In two-dimensional mode, the programmable K-parameter (k – 1 to 255 and infinity) defines the number of lines to be encoded in 2-0 coding sequence before a 1-D line is inserted. For error free environments (Group 4) K Infinity allows for maximum compression. The CEP can address up to 16 Mbytes of memory on each bus and two butters (Seems and destination) on both the compressor and expander. Starting address, buffer length and current address for image and coded data are stored in internal registers independently for both the compressor and expander.
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