EP900DC

The Altera EP900 Is a pin-compatible version of the popular EP910 Erasable Programmable Logic Device (EPLD), Available in 40-pin DIP and 44-pin J-leaded chip carrier packages, the EP900 contains 24 Macrocells with user-configurable I/O architec-ture, allowing up to 36 inputs and 24 outputs. Each of the 24 Macrocells contains a program-mable AND and fixed OR PLA structure, see Figure 1, with a maximum eight product terms for logic implementation. In addition, single product terms control Output Enable/Asynchronous Clock and Asynchronous Clear functions, The Altera proprietary programmable I/O archi-tecture allows the EP900 user to program output and feedback paths for both combinatorial or registered operation, active high or active low. For increased flexibility, the EP900 also includes programmable registers. Each of the 24 internal registers may be programmed to be D, T, SR or JK flipflop. In addition, each register may be clocked asynchronously on an individual basis or syn-chronously on a banked register basis. For proper operation, standard high performance design practices should be followed. It is recom-mended that opaque labels be placed over device window. Input and output pins must be constrained to the range GND < (VIN or VouT) 5_ Vcc. Unused inputs must always be tied to an appropriate logic level (e.g. either Vcc or GND), Each set of Vcc and GND pins must be shorted together directly at the device, Power supply decoupling capacitors of at least .2pF must be connected between each Vcc pin and GND. For the most effective decoupling, connect one capacitor between each set of Vcc and GND pins, directly at the device. Programming the EP900 is accomplished by using the Altera A+PLUS PC-based development software which supports schematic capture, net-list, state machine and Boolean equation design entry methods. Once the design is entered, A+PLUS automatically performs translation into logical equations, Boolean minimization, and de-sign fitting directly to an EP900. The device may then be programmed to achieve customized work-ing silicon within minutes at the designer’s own desktop. For full EP900 functional description please consult the EP910 datasheet.